Greater Integration Between the SCADA and DMS

Moves towards a smarter grid are seen in the form of greater integration between the SCADA and DMS throughout the transmission network and medium-voltage equipment. Moreover, as utilities roll-out Advanced Metering Infrastructure (AMI), the integration of AMI data with the DMS is a defining aspect of the smart grid. The integration of AMI data with DMS applications is expected to deliver benefits such as shorter outage duration, better management of system loading, and improved voltage profiles. From the customer’s perspective, smart meters are intended to increase awareness of energy usage, including real-time and historical information, which should help reduce overall energy consumption. This simplifies network-management challenges for utility companies, while empowering consumers to reduce their own energy bills.

Smartening the distribution network

A growing number of smart devices are being installed in substations and distribution systems. These include intelligent controls for voltage regulators used for volt/VAR control, and line reclosers and switches used for tasks such as automatic switching, fault isolation, and automatic restoration after temporary faults.

The use of serial communication protocols for communicating with intelligent controllers, or integrated devices such as smart reclosers, is giving way to Ethernet-based networking using the latest IEC 61850 communication standard. In addition to promoting interoperability and eliminating protocol diversity, IEC 61850 incorporates the GOOSE (Generic Object Oriented Substation Events) protection-speed messaging protocol, which enables high-speed protection, transfer switching, fault isolation, and service restoration. The high speed of the GOOSE protocol allows intelligent controllers or smart reclosers communicating on a peer-to-peer basis to identify the location of a fault, and therefore avoid the voltage disturbances caused by repeated actuation of conventional reclosers. When the fault is pinpointed, the operator can take the correct remedial action to restore service and repair the fault.

To implement comprehensive measurement, protection and automation functionalities at the recloser level, multiple voltage sensors and current transformers are required. Current transformers are used to measure the current in each phase accurately. CR Magnetics has a range of commercial and metering-class current transformers, which can be used for various monitoring and fault-detection duties and includes devices rated up to 4000 A. The metering-class transformers provide high accuracy and minimum phase-angle error. Current transformers allow non-contact monitoring of the current in a conductor by passing the conductor through the transformer’s central window. The CR Magnetics range features square and circular current transformers including the CR7310, which can be used for detecting ground faults or other causes of 3-phase imbalance. All three phases and neutrals are routed through the transformer window, and the sum of the 3-phase Y currents is expected to be zero when the loads are equal. If there is an imbalance, the phases do not cancel and the relay trips.

Smart meters reach the customer

While IEC 61850 communication over Ethernet is becoming more widely used at the substation and feeder level, power line communication (PLC) using a protocol such as IEC 61334, PRIME (PoweRline Intelligent Metering Evolution), or G3-PLC enables utilities to leverage their existing power line infrastructure to communicate with smart meters installed at customer premises. Low-frequency narrowband PLC is typically used, at frequencies up to 500 kHz.

The underlying functional elements of a smart meter, which comprise analog measurement, processing and communications, may be implemented using discrete Analog Front-End (AFE), processor and communication modem components, or using a more integrated approach.

Texas Instruments’ TMS320F28 PLC microcontroller seeks to simplify design while preserving flexibility by integrating the PLC modem functionality and providing a development platform including a PLC modem hardware-configuration tool and the plcSUITE™ software framework. This platform allows developers to quickly develop and test robust PLC implementations and provides flexibility to separate the modulation implementation, the protocol design, and the development of the application. The platform provides a graphical user interface that helps developers visualize and fine-tune key PLC modem performance parameters. Combined, this modular hardware architecture and flexible software framework creates the industry’s only PLC technology capable of supporting multiple standards and modulation schemes with a single platform. Developers can use this platform to create a variety of PLC solutions for smart-energy applications, as shown in Figure 2, with the flexibility to adapt as the applicable standards evolve.

Figure 2: PLC technology is ideal for a wide range of smart-energy devices for consumer, municipal, and transmission applications.

STMicroelectronics has combined processing functionality, PLC modem, and analog front-end into a single System-on-Chip (SoC) device in its STarGRID family of PLC SoCs. As Figure 3 illustrates, the STarGRID platform includes an 8051 processor core for protocol control duties, combined with a separate DSP, giving the flexibility to support multiple modulation schemes. The power line driver, analog front-end, and auxiliary functions such as power and clock management are also integrated. The family of devices includes the ST7580, which is currently being used in 13 million smart meters by the utility companies ENEL and ENDESA, which have operations in southern Europe and Latin America. A similar device, the ST7590, is certified by the PRIME Alliance and used by the Spanish energy group Iberdrola in the 11 million meters deployed as part of its STAR project.

Figure 3: Key functional elements of the STarGRID® narrowband SoC platform.

Controlling the new functionality

The design of today’s electronic smart meters takes advantage of remote communications, via PLC or wireless, to implement features and capabilities that have not been possible with traditional electromechanical meters. Among these is the service-disconnect switch, which is used to disconnect a property from the grid for safety reasons such as if the premises are unoccupied or during maintenance or emergencies. By integrating this function as an electronically-controlled switch in the smart meter, it can be actuated from a remote location. This not only allows safety or emergency disconnect instructions to be carried out quickly and efficiently, but also gives utility companies extra flexibility to manage demand and maintain grid stability and voltage levels. The switch is typically a dual-coil polarized latching relay, which requires no holding current to maintain the contacts in either an open or closed state. To ensure reliable delivery of relay-control pulses generated by the microcontroller, and minimize the possibility of tampering, a suitable relay driver such as the Fairchild Semiconductor FAN324x may be used. The FAN3240 has outputs rated for operation from 8 V to 60 V, and integrates a filter/timer block that prevents inadvertent switching from noisy input signals.

Conclusion

The transition to a smart grid is an ongoing process that applies to the entire electricity transmission and distribution network, and has already been taking place for some time. Distribution companies have been using data from SCADA in progressively smarter ways, and driving SCADA further into the network in pursuit of the same goals that are associated with the smart grid as it is understood today. Smart meters capable of providing richer data both to utilities and consumers, represent the final link, bringing smart technology into customers’ premises and general public awareness.

http://www.digikey.com/en/articles/techzone/2013/nov/keeping-the-smart-grid-smart

Achieving Better Embedded Software Performance Through Memory Layout Optimization

Software Engineering for Embedded Systems, Mike Brogioli of Polymathic Consulting provides tips on various memory layout optimization techniques that can be used to improve embedded system performance.

In order to obtain sufficient levels of performance, application developers and software systems architects must not only select the appropriate algorithms to use in their applications, but also the means by which those applications are implemented. Quite often this also crosses the line into data structure design, layout and memory partitioning for optimal system performance.

It is true that senior developers often have insight into both algorithms and their complexity, as well as a toolbox of tips and tricks for memory optimization and data structure optimization. At the same time, the scope of most embedded software engineering projects prohibits manual code and data hand optimization due to time, resource and cost constraints.

As such, developers must often rely on the tools as much as possible to optimize the general use cases, only resorting to hand-level tuning and analysis to tweak performance on those performance-critical bottlenecks after the initial round of development.

This last round of optimization often entails using various system profiling metrics to determine performance-critical bottlenecks, and then optimizing these portions of the application by hand using proprietary intrinsics or assembly code, and in some cases rewriting performance-critical kernel algorithms and/or related data structures. This article follows on from the topics discussed in Part 1 and details design decisions that may prove useful for embedded system developers concerned with the issues those topics mentioned above.

Overview of memory optimization
Memory optimizations of various types are often beneficial to the run-time performance and even power consumption of a given embedded application. As was mentioned previously, these optimizations can often be performed to varying degrees by the application build tools such as compilers, assemblers, linkers, profilers and so forth. Alternatively, it is often valuable for developers to go into the application and either manually tune the performance or design in consideration of memory system optimization a priori, for either given performance targets or so as to design the software architecture to be amenable to automated-tool optimization in subsequent phases of the development cycle.

In tuning a given application, quite often the baseline or “out of box” version of the application will be developed. Once functionality is brought online, the development team or engineers may select to profile the application for bottlenecks that require further optimization. Often these are known without profiling, if certain kernels within the application must execute within a given number of clock cycles as determined by a spreadsheet or pen and paper exercise during system definition. Once these key kernels are isolated or key data structures are isolated, optimization typically begins by those experts with knowledge of both software optimization techniques, compiler optimizations, the hardware target and perhaps details of the hardware target instruction set.

Focusing optimization efforts
Amdahl’s law plays an interesting role in the optimization of full application stacks, however, and is not always appreciated by the software system developer. If only 10% of the dynamic run-time of a given application can benefit from SIMD or instruction-level parallel optimizations versus the 90% of dynamic run-time that must be executed sequentially, then inordinate amounts of effort on parallelizing the 10% portion of the code will still only result in modest performance improvements. Conversely, if 90% of the total application’s dynamic run-time is spent in code regions exhibiting large amounts of instruction-level parallelism and data-level parallelism, it may be worthwhile to focus engineering effort on parallelizing these regions to obtain improved dynamic run-time performance.

In determining those portions of the code which dominate the dynamic application run- time, and may be the best candidates for either hand optimization or hand adjustment for applicability to automated-tool optimization, application developers typically use a software profiler in conjunction with either the silicon target or software-based system simulation. Intel’s VTUNE is one such example of a profiling framework; alternatively the GNU GCC compiler and GPROF are open-source solutions that provide dynamic run-time information. Many silicon vendors such as Freescale Semiconductor and Texas Instruments also offer their own proprietary solutions for use with their respective silicon targets, allowing for either traces collected on software-based simulation platforms, or alternatively larger application-level traces that can be collected on the native silicon target.

Vectorization and the dynamic code: compute ratio
Vectorization of loops is an optimization whereby computation performed across multiple loop iterations can be combined into single vector instructions, effectively increasing the instruction-to-compute ratio within the application’s dynamic run-time behavior. Consider the example in Figure 5.

     short a[16], b[16], c[16];
     for(iter=0; iter<16; ++iter)
     {
          // results in single 16-bit MPY instruction
          // generated in assembly listing
          //
          a[iter] = b[iter] * c[iter]
     }

     short a[16], b[16], c[16]; for(iter=0; iter<16 iter+=4)
     {
          // with high level compiler vectorization,
          // results in 4-WAY parallel 4x16-BIT multiply
          // vector instruction, effectively performing the
          // computation of four iterations of the loop in
          // a single atomic SIMD4 instruction.
          //
          a[iter:iter+4] = b[iter:iter+4] * c[iter:iter+4];
     }

Figure 5: Loop level vectorization example

In the first loop nest, we can see that each iteration of the loop contains a single 16-bit by 16-bit multiply instruction whose result is written to the a[] array as output. One multiplication instruction is performed for each iteration of the loop, resulting in 16 16-bit multiplications. The second loop, however, shows pseudocode for how the compiler or application developer might vectorize the loop when targeting an architecture that supports a four-way SIMD multiply instruction over 16-bit integer elements.

In this case, the compiler has vectorized multiple iterations of the loop together into the multiply instruction, as denoted by the array[start_range:end_range] syntax denoted in the second loop nest. Note that the loop counter is incremented by the vectorized length for each iteration of the loop now. Clearly only four iterations over the loop are now needed to compute the resulting an output array, as each iteration of the loop now contains a single vector multiply instruction that computes four elements of the output vector in parallel.

There are many benefits to vectorizing code in this manner, either by hand if the application developer uses intrinsics that are proprietary with respect to the target architecture, or if the compiler is able to vectorize the code. One such benefit is the increase in performance, as the code now exploits dedicated SIMD hardware, often providing a multiplication in improvement over the vectorized loop on the order of the underlying SIMD vector hardware.

Other benefits are the reduction in code size, as loops are no longer unrolled resulting in explosions in the code size, but rather more dense instructions of vector format are used rather than atomic scalar instructions. This may have secondary benefits in reducing the number of instruction fetch transactions that go out to memory as well. Lastly, the overall ratio of dynamically issued instructions to computation performed within the application is increased as well.

There are a number of challenges to both the development tools and the application developers when trying to vectorize code at the loop level. One such challenge is the code shape of loop nests that are candidate for vectorization. Typically, build tools need to understand the loop iteration space of a loop, so using constant loop bounds rather than run- time computed values may be beneficial depending on the advancement of the underlying compiler’s vectorization technology.

Secondly, the types of computation performed within the loop nest must be amenable to vectorization. For example, in the example above simple 16-bit integer multiplication is performed for a target architecture supporting a supposed 16-bit four-way SIMD multiply instruction. If the underlying target architecture only supports 8-bit SIMD multiplication, it may be advantageous to avoid 16-bit multiplication wherever possible if vectorization is desired.

Loop dependence analysis is another concern when vectorizing or parallelizing loop nests, as the compiler must be able to prove the safety of loop transformations. Loop dependence analysis is the means by which the compiler or dependence analyzer determines whether statements within a loop body form a dependence with respect to array accesses and data modifications, various data reduction patterns, simplification of loop-independent portions of the code and management of various conditional execution statements within the loop body.

As an example, consider the fragment of C-language code in Figure 6.

     for(iter_a=0; iter<LOOP_BOUND_A; ++iter_b)
        for(iter_b=0; iter_b<LOOP_BOUND_B; ++iter_b)
           a[iter_a+4-iter_b] =
              b[2*iter_a-iter_b]+ iter_a*iter_b;

Figure 6: Fragment of C language code

For the loop above, the compiler’s data dependence analyzer will attempt to find all dependences between the statements reading the array b[] and writing to the array a[]. The challenge for the data dependence analyzer is to find all possible dependences between the statements that write to array a[] and read from array b[]. To ensure safety, the data dependence analyzer must ensure that it can explicitly prove safety or, in other words, any dependence that cannot be proven false must be assumed to be true to ensure safety!

The data dependence analysis shows independence between references by proving that no two instances of statements to array a[] and array b[] access or modify the same spot in array a[]. In the event that a possible dependence is found, loop dependence analysis will make an attempt to characterize the dependences, as some types of optimizations over loop nests may still be possible and profitable. It may also be possible to further transform the loop nests so as to remove the dependence.

In summary, writing loop nests so that a minimum of data dependencies exists between array references will benefit vectorization and other loop transforms as much as possible. While the compiler technology used in analyzing data dependencies and autovectorizing serial code for vector hardware stems from the supercomputing community, improperly written code with troublesome data dependencies and loop structure may still thwart the vectorization efforts of the most advanced tool sets.

At a high level, simply writing code which is easiest for humans to understand usually produces code that is easiest for the vectorizer to understand as well, as the vectorizer and data dependence analyzers can easily recognize what the programmer intended. In other words, highly hand-tuned code with a priori knowledge of the underlying target architecture is not the best candidate for automated vectorization at the tools level.

There are a number of things that application developers may want to keep an eye out for when developing code with the intent of autovectorization by the build tools.

Pointer aliasing in C
One challenge for vectorizers and data dependence analysis is the user of pointers in the C language. When data is passed to a function via pointers as parameters, it is often difficult or impossible for the data dependence analyzer and subsequent vectorizer to guarantee that the memory regions pointed to by the various pointers do not overlap in the interaction spaces of the loops in which they are computed. As the C standard has evolved over time, support for the “restrict” keyword has been added, as can be seen in the example in Figure 7.

     void restrict_compute(restrict int *a, restrict int
     *b, restrict int *c)
     {
          for(int i=0; i<LIMIT; ++i)
               a[i] = b[i] * c[i];
     }

Figure 7: C Standard “restrict” keyword

By placing the restrict keyword qualifier on the pointers passed to the procedure, this ensures to the compiler that the data accessed by a given pointer with the restrict keyword does not alias with anything else the function may modify using another pointer. Note that this only applies to the function at hand, not the global scope of the application itself. This permits the data dependence analyzer to recognize that arrays are not aliased or modified by references with other side effects, and allows more aggressive optimization of the loop nest including vectorization amongst other optimizations.

Source:-http://www.embedded.com/design/debug-and-optimization/4436459/Achieving-better-embedded-software-performance-through-memory-layout-optimization-Part-2                        

Sensor Fusion Goes Open-Source

AUSTIN, Texas – Analog Devices, Freescale, PNI Sensor Corp., and the MEMS Industry Group formed the Accelerated Innovation Community, a group dedicated to providing open-source algorithms for sensors. AIC also plans to announce an I/O standard for sensors in collaboration with the MIPI Alliance.

Engineers shouldn't have "to reinvent the wheel on common algorithms every time they want to add or change functionality in their product," said Karen Lightman, executive director of the MEMS Industry Group (MIG). "Access to an open-source library of introductory algorithms fundamentally changes the development paradigm."

Freescale was an early catalyst of AIC and has added open-source algorithms such as a C source library for 3-, 6- and 9-axis sensor fusion. Sensor fusion is a basic building block for sensor data analytics and for motion tracking, said Freescale's Ian Chen.

"It's all about bringing the relevant data together from multiple sensors to provide a bigger picture of what's going on in a system," Steve Whalley, chief strategy officer at MIG and a former director of sensors at Intel, told EE Times. AIC aims to let engineers "focus their own real differentiating capabilities on the more complex algorithms that are needed for today's products above and beyond the introductory algorithms in the AIC."

Steve Whalley

The key challenge in sensor fusion is effectively separating signal, motion, and noise, Chen said. AIC's algorithms aim to take redundant data from different sensors that observe the same event to distinguish between noise and signals, then compute more accurate information.

"Sensor fusion encompasses a variety of techniques which leverage the inherent strengths and monitoring that these individual sensors do to achieve more accurate results than the individual components could achieve by themselves," Chen told EE Times.

Source:-http://www.eetimes.com/document.asp?doc_id=1324503&

Synopsys Simplifies Low Power Lot Sensor & Controller Soc Design

Synopsys, Inc. has just released a complete hardware and software IP building block optimized for a wide range of ultra-low power embedded sensor and control applications.


"Embedded sensor and control applications require a high level of integration with minimal power and area," said John Koeter, vice president of marketing for IP and Prototyping at Synopsys.

To achieve this goal, he said, the company's Sensor and Control IP Subsystem integrates the DesignWare ARC EM4, EM6, EM5D or EM7D 32-bit processors, delivering efficient real-time control and DSP performance required for ultra-low power sensor- and control-based applications.
Newly integrated peripherals include a UART for serial communication as well as a Pulse Width Modulation (PWM) block and Digital-to-Analog Converter (DAC) interface for actuator/motor control functions.

An optional IEEE 754-2008 compliant floating point unit (FPU) reduces energy consumption by up to 10X for sensor fusion applications implementing floating point operations. He said designers using the DesignWare building block are provided with a pre-verified, SoC-ready IP subsystem that delivers the energy- efficient processing required in markets such as the Internet of Things (IoT).
Koeter said the subsystem is designed to process data from digital and analog sensors and always-on audio sources with minimal power consumption. "This enables offloading of the host processor and more efficient processing of the data,

" he said.
The fully configurable subsystem includes the choice of an ARC EM4, EM6, EM5D or EM7D processor. All the processors support up to 2 MB of closely coupled memory (CCM) for both instruction and data, while the EM6 and EM7D also incorporate up to 32 KB of instruction and data cache for maximum system performance and flexibility.

The EM5D and EM7D provide developers with a high-efficiency control and signal processing capability that gives them access to more than 100 DSP instructions. Included in the subsystem are integrated UART, PWM and ARM AMBA APB interface peripherals combined with the configurable GPIO, SPI, I2C and ADC/DAC interfaces for a variety of off-chip sensor and actuator connections.

Targeted at designs where it is necessary to process the extensive amount of data in sensor fusion applications, the subsystem includes a rich library of off-the-shelf DSP functions supporting filtering, correlation, matrix/vector, decimation/ interpolation and complex math operations.

"Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP instructions within the EM5D or EM7D processor and tightly coupled hardware accelerators," said Koeter, "to boost performance efficiency and reduce power consumption by up to 85 percent compared to discrete solutions. "

An optional IEEE 754-2008 compliant FPU reduces energy consumption by up to 10X for sensor applications requiring single- or double-precision floating point operations. Additionally, the ARC Processor EXtension (APEX) technology enables designers to add their own user-defined instructions or existing hardware to the processor. 

ICS-CERT warns BlackEnergy malware attacking SCADA system HMI

The US Department of Homeland Security's Industrial Control System Cyber Emergency Response Team (ICS-CERT) has just issued an alert about malware that is targeting human-machine interfaces (HMIs) of industrial control systems. https://ics-cert.us-cert.gov/alerts/ICS-ALERT-14-281-01A.


It is based on a varient BlackEnergy malware toolkit malware that infects HMIs on any supervisory control and data acquisition system (SCADA) that has a direct connection to the Internet. It is a continuation of a malware campaign targeting numerous companies that has been ongoing since 2012.

In applications where an ability to remotely monitor or operate the system is required, the SCADA/HMI is often connected to the public Internet as the link to the remote operator. It is such installations that the BlackEnergy malware has been attacking the alert warns.

So far, the report lists three commercial SCADA/HMI software products are listed in ICS-ALERT-14- 281-01A, including GE Cimplicity, Advantech/Broadwin WebAccess, and Siemens WinCC for SIMATIC.

The ICS-CERT analysis indicates the attack involves making an HMI server run a malicious screen file hosted on an attacker-controlled server, which then installs the malware. According to the alert "at this time, ICS-CERT has not identified any attempts to damage, modify, or otherwise disrupt the victim systems’ control processes."

Howver, ICS-CERT warns that this kind of malware usually searches for removable media and network-connected file shares that can provide a pathway into the target company's computer networks.

Source:http://www.embedded.com/electronics-news/4436970/ICS-CERT-warns-BlackEnergy-malware-attacking-SCADA-system-HMIs

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Research and Markets: Industrial Automation Control (DCS, PLC, MES, APC & SCADA) Market in the Americas 2014-2018

Web-based automation solutions provide complete real-time information from production plants, which increases the production process. A web-based automation solution integrates with various production plants at the shop floor level and shares the information gathered through a common database. Thus, it helps improve the decision-making system and reduces the total cost of ownership. Therefore, the cost-effectiveness of this solution is expected to enhance the demand for web-based automation solutions in many cost-sensitive industries.

According to the report, the need to improve the decision-making process across industries is one such driver. Real-time delivery of accurate operational information offered by industrial automation solutions aids the decision-making process of plant engineers.

Further, the report states that an automation solution requires significant investment, not only for installation, but also for regular upgrades, and integration and support. Therefore, the overall cost of adopting these solutions is very high.

The study was conducted using an objective combination of primary and secondary information including inputs from key participants in the industry. The report contains a comprehensive market and vendor landscape in addition to a SWOT analysis of the key vendors.
Industrial automation systems include five major types:

• DCS
• PLC
• MES
• APC
• SCADA.

Key Vendors

• ABB Ltd.
• Honeywell International Inc.
• Rockwell Automation Inc.
• Siemens AG

Other Prominent Vendors

• Applied Material Inc.
• Apriso Corp.
• Aspen Technologies Inc.
• Camstar Systems Inc.
• Control Systems International Inc.
• Emerson Electric Co.
• Eyelite Inc.
• GE Co.
• Invensys plc
• Metso Corp.
• Miracom Inc.
• Mitsubishi Heavy Industries Ltd.
• Omron Corp.
• SAP AG
• Schneider Electric SA
• Toshiba International Corp.
• Werum Software & Systems AG
• Yokogawa Electric Corp.

Key Topics Covered:

1. Executive Summary
2. List of Abbreviations
3. Scope of the Report
4. Market Research Methodology
5. Introduction
6. Market Landscape
7. Market Segmentation by Product
8. Market Segmentation by End-users
9. Buying Criteria
10. Market Growth Drivers
11. Drivers and their Impact
12. Market Challenges
13. Impact of Drivers and Challenges
14. Market Trends
15. Trends and their Impact
16. Vendor Landscape
17. Key Vendor Analysis       

Source:-http://www.businesswire.com/news/home/20140716005875/en/Research-Markets-Industrial-Automation-Control-DCS-PLC#.VF2c8mf6y1s

Instrumentation Engineering in Demand | Training With Sofcon

100% Placement Assistance

Nature of work of an instrumentation engineer ranges from designing, developing, installing, managing equipments that are used to monitor and control machinery, finds Sumit Bhattacharjee

Just imagine a world without instruments. It would be like traversing into a time that probably goes even beyond the Stone Age. Man has always been fascinated towards instruments and the quest to invent and innovate on new instruments has pushed mankind beyond barriers to an age where instruments have become a part and parcel of the life. Today, we find instruments at home and at workplace, and this was possible only because of the science instrumentation.

In scientific terms, instrumentation is defined as the art and science of measurement and control of process variables within a production, or manufacturing area. The science has further opened up the realm of instrumentation engineering.

The discipline of instrumentation engineering branched out of the streams of electrical and electronic engineering some time in the early part of 1970s. “It is a multi-disciplinary stream and covers subjects from various branches such as chemical, mechanical, electrical, electronics and computers,” says Prof. A. Bhujanga Rao, from the department of Instrumentation Engineering, Andhra University.

The professor adds that instrumentation engineering is a specialised branch of electrical and electronic engineering and it deals with measurement, control and automation of processes.

Scope

Almost all process and manufacturing industry such as steel, oil, petrochemical, power and defence production will have a separate instrumentation department, which is manned and managed by instrumentation engineers. “Automation is the buzz word in process industry, and automation is the core job of instrumentation engineers. Hence, the demand for instrumentation will always be there,” says the professor.

The growth in the avionics, aeronautical and space science sectors has also increased the scope for instrumentation engineers. Instrumentation engineers can also fit in both software and hardware sectors.

Apart from covering core subjects such as system dynamics, industrial instrumentation and process control, analytical and bio-medical instrumentation and robotics, the students deal with software and hardware topics such as microprocessor and micro controller based instrumentation, VLSI and embedded system designs, computer architecture and organisation and computer control of processes. Computer languages such as ‘C' and Fortran are also part of the curriculum. 

This makes an instrumentation engineer fit for both the hardware and the software industry. Moreover, since instrumentation engineers are presumed to be good in physics, the logical ability is expected to be on the higher side, which is a basic quality needed to excel in the software industry.

The demand is so high that every student finds at least two jobs waiting in the wings, by the time he or she completes her course, says Dr. Bhujanga Rao.

Nature of work of an instrumentation engineer ranges from designing, developing, installing, managing equipments that are used to monitor and control machinery and processes.

“Though there is a demand for instrumentation engineers from the software sector, we prefer the core area, as that is where we can showcase our creativity and knowledge,” says Srinivas a third-year student.

The shift towards core sector is not only due to the opportunity to showcase ones creative talent and knowledge, but also because of the long term stability and quick growth. Bio-medical is another area that is fast catching up and there is huge requirement for instrumentation professionals.

Instrumentation engineering that made its way as an exclusive engineering discipline in the early part of 1970s was earlier known as M.Sc. Tech Instrumentation in many of the colleges. It was then a three-year PG course. Even today, it is referred to by different names by various colleges. While some call it as B. Tech- electronics and instrumentation, a few name it as B. Tech – control and instrumentation. Whatever, be the name, the curriculum is the same. 

Source:-http://www.thehindu.com/features/education/instrumentation-engineering-in-demand/article3320296.ece

Top 10 Indian Embedded Companies

It has been over two years since I wrote the piece — Top 10 embedded companies in India! It has been the most read, and by far, the most commented.  Now, it is time to do a review, or, more suitably, a recap!

First, who are the top 10 (Indian) embedded systems and software companies in India? My list, in no particular order, would read something like this:

1. Ittiam
2. Sasken
3. Sofcon
4. C-DAC
5. L&T EmSyS
6. ProcSys
7. eInfochips
8. Mistral
9. iWave Systems/Global Edge
10. Vayavya Labs

There are several firms in Pune and Hyderabad, who probably deserve a name.  There may be some folks may not agree with this list, but I would go with these, for now. The next change could be two years down the road!

Some may even question the presence of Sofcon System and C-DAC in this list. However, Sofcon has well over 30+ years of extensive experience in providing consulting, design and development services and testing services in real-time systems.

C-DAC has capabilities in high-performance computing as well as grid computing. It also has unit focusing on professional electronics, including embedded and VLSI products.

Ittiam and Sasken remain in the top 5 category. ProcSys is a new entrant, besides iWave, Global Edge and Vayavya Labs.

Now, may I know if you have any doubts, as well as moves, additions and/or changes (MAC)?

Status of Power Semiconductor Devices Industry

There are more available solutions than ever in power devices, according to Alexandre Avron, market and technology analyst, Yole Développement.

The landscape is moving, and its moving quite fast, from every region of the world.

There are many opportunities for power device manufacturers. This is the time for strong strategic planning and making the best choices.
He was speaking at a seminar on the power semiconductor devices industry, in Lyon, France.
IGBTs and SJ MOSFETs
Silicon is not dead and will still live for a long time. Standard device design are slowly disappearing (planar IGBT, planar MOSFET). IGBT and SJ MOS are highly mature technologies. Rules of competition are evolving.

Historic players need to keep on innovating. New entrants have a different business model: there are more and more foundries, with fab-less and fab-light players. IGBT is still a key asset: master and secure IGBT supply is necessary for system makers. SJ MOSFETS will be used in more and more systems, taking market shares to planar MOSFET.

About SiC and GaN, there is still a big question mark: Where and when? With time, it is becoming clearer. SiC will target medium and high power. From our point of view, medium power (1200V base) is a mean to arrive to high power (+3.3kV). R&D has to go through this to reach higher voltage. The main issue is still on current ratings (having a high impact on cost).

GaN will target low and medium power, and will probably allow extraordinary power supplies designs (Tiny supplies, very high frequency systems). It is almost ready for 600V, but not yet at 1200V. It leaves room for SiC to develop and expand.

Major players are involved on both fields — SiC and GaN. They need to be present on both domains, as there will be an overlap, but the split is unclear: we will probably experience a very fine segmentation, not only by voltage or current, but also by frequency, ruggedness, system size, temperature of operation or maybe culture or history.

SiC is now here. First full SiC PV inverters are available. First field tests for SiC in rail traction is ongoing. GaN is under qualification. According to the most advanced players, 600V GaN devices samples are tested by system makers.


Infineon and ST Microelectronics are the undisputed leaders in power devices. Asian and American players want to gain market shares to compete with Infineon and ST.

IGBTs main applications can be divided in six market segments – rail traction, wind turbines, UPSs, PV inverters, motor drives and EV/HEVs. Smaller market segments include:

* Other industrial systems (welding, heating).
* Consumer (camera flash, induction, power supplies).
* Medical, military, aerospace, automotive.

Many players entered the market in the last 24 months. It may be the first signs of maturation, and generalization of super junction MOSFETs. Planar MOSFETs presence would then decline. SiC diodes today are already in production, mainly coupled with IGBT technology. Penetration of SiC in wind turbines will happen later than expected. For all other segments, Yole Développement roadmaps have been confirmed.


Next step for large production SiC-based devices will be JFETs; MOSFETs will come later. Keep in mind that today, product availability, price and test results are not in line with inverter maker’s expectations. GaN is on its way to being available: The manufacturers, perhaps, did not want to do early announcements (as for SiC), and will then follow their roadmaps.

Growing Indian Power Electronics Market Provides Host of Opportunities

In case you are an enterprenuer, or an aspiring one, in electronics and wish to invest or manufacture in the sector, but don’t know where to go, here’s a welcome relief — in form of a report on the power electronics sector in India.

The India Power Electronics Market Report – 2010 has been developed by Dhaval Dalal and Ram Kumar, on behalf of Innovatech Switching Power India Pvt Ltd in Bangalore, India. I was delighted on being contacted by Ram Kumar, MD, who was kind enough to share some bits of this report.
The unprecedented growth in the Indian electronics demand (estimated at $50 billion for 2009), has spawned a corresponding spurt in the domestic power electronics industry. While this growth has been acknowledged in industry circles, no specific data exist to understand this phenomenon – this report aims to fulfill this gap.

The report highlights the peculiarities of Indian industry by identifying unique areas of growth which require special attention from industry participants. It also highlights the gap between the domestic demand and supply which is currently fulfilled by imports. Conversely, areas where the Indian industry contributes to the global demand by exporting products/services are also highlighted.
Coming from technology/strategic marketing background and with an unmatched access to the decision makers and trendsetters in Indian electronics industry, the authors are able to provide a highly credible and comprehensive account of the market that goes well beyond the surface data and helps identify actionable agenda for the reader.

So, here’s an opportunity for folks to enter the Indian power electronics segment, which offers a host of opportunities.

Some excerpts from the report are reproduced here.

Energy segment in India
Power backup (including batteries) is a $1.1 billion revenue industry in India. This industry has several facets uniquely shaped by Indian market realities of customer need and supply-demand dynamics. Two types of power backup devices commonly deployed in India are (a) the UPS; and (b) the inverter.
In the Indian context, the UPS systems refers to a power backup source for limited times, up to one hour or less, and a true-sine wave output is generated.

These are generally on-line systems where power is processed continuously and no „transition‟ to backup mode is seen by the load. Desktop computers, data centers, hospitals, telecom exchanges, and mission critical applications use UPS systems. Battery ratings are consequently lower and form less than 30 percent of the system cost. One of the reasons for shorter back-up time is that there is an alternative power generation source (such as diesel generator), that comes on-line soon after utility power fails.

The inverter system refers to a power backup source for extended time of power outages, typically from one hour to eight hours or more, and a pure sine-wave output (older products produce quasi-sine wave output) is produced by the system. Battery ratings (and the battery chargers also) are typically of high capacity, consequently the battery costs can form 60 percent or more of the system cost. These are popularly deployed in homes and offices to drive ceiling fans, TV sets, fluorescent and incandescent lights, or even elevators in housing complexes during power outages.

One salient characteristic of these applications is that they are essentially power electronics end equipment, and hence, power electronics is the driver and forms a large portion of the cost of the system. We estimate the power electronics content in the UPS and inverter markets combined at $494 million per year.

Demand and growth rates for power backup systems
The figures provide unit volume and PE content for power backup segment in 2009.

Report on India power electronics market by Innovatech Switching Power India Pvt Ltd.

UPS systems
We estimate the UPS market in India has a power electronics content of $290 million. The industry has seen declining revenues the past two years of 8-9 percent, but prior to 2008 the industry grew at a CAGR of 18 percent+ for five to six years.

The sub-5 kVA systems make up 35 percent (by unit volume) of the UPS and Inverters sold in India‟s market. Within this, more than 70 percent by unit volumes shipped are rated 600 VA and below, which cater to the desk-top computer and linked to the growth of this market. Recent growth in the penetration of laptops and net books and the erosion in desktop PC sales are perceived as the reason for declining sales in 2009 in the 600 VA and below segment. The 10-100 kVA systems earn the highest revenues in the online and line-interactive UPS systems market.

The outlook for 2010 remains depressed to flat, and beyond that recovery to a CAGR of 18-20 percent is our forecast given the power shortage in the country. Several projects for generating power, largely coal-fired plants, are in the pipeline and a recent initiative to tap into solar power has begun, however, this power hungry nation will still see power outages due to the supply-demand gap in power generation for the near future.

Inverters
We estimate 1.8 Mu inverters are sold annually in India, with more than 60 percent rated below 1.5 kVA. We estimate the power electronics content at $204 million. This market is expected to remain steady in 2010 and accelerate to a growth of 10-15 percent as the power shortage in the country is expected to ease only after 2012. This industry is currently much more fragmented than the UPS industry.

The unbranded inverter industry in India is estimated to have a power electronics content of $60 million, and more than 80 percent is sourced from China/Taiwan presently. Cost pressures are at the root of this trend and manufacturers tend to become traders in this high volume business segment. Unless significant policy changes happen to encourage access to low cost components for the local manufacturing industry, the trading opportunity will remain attractive.

Interested folks can buy the report from Innovatech for $1,495; or Rs 65,000 plus taxes.
India will surely benefit from more such industry reports as these would definitely help grow the Indian electronics ecosystem.

Top 10 Companies in India Who Use Embedded Systems | Sofcon Embedded Training

Right then! This topic should be of interest to several folks in India as well as overseas! Especially, those who are looking to tap the renowned Indian talent in embedded systems and software.

It is very well known that all the leading MNCs are present in India, and well, do great work in embedded systems and software. Definitely, any top 10 list of such companies would include the likes of:

* Intel
* Texas Instruments
* Freescale
* Philips
* Samsung
* LG Electronics
* And some of the other leading multinational companies.

However, my exercise is NOT to look for the leading MNCs in this domain, but to find out who are the leading Indian companies ‘working’ in the embedded systems and software space.

Some immediate ones that would spring to mind could be the likes of Ittiam, Sasken, Mistral, KPIT, Symphony, Mphasis, eInfochips, Infosys, TCS, HCL Technologies, Wipro, etc., perhaps.
There are so many others, including Yindusoft, Dexcel Designs, Ample Communications. Ibex, EmLabs, eSpark Infotech, i Micro System, Adamya Computing, etc.

However, I am not very sure how all of these companies are currently performing, nor is it possible for me to find out in a short time. Nevertheless, having been in close touch with some of these companies, it is quite possible that the downturn could be hitting some of the smaller companies, and maybe, even the bigger ones.

Well, it is a downturn after all, and spends are not that high!

It is widely hoped that the very strong Indian embedded industry will overcome these problems and shine brightly in the new year.

In my list of the leading Indian companies in the embedded space, I am clubbing some of the larger companies, which are also into other activities, such as IT and outsourcing services.

In no particular order, my top 10 companies in the embedded systems and software space in India would be:
1. Tata Elxsi/Sasken
2. Ittiam Systems
3. Infosys/TCS
4. HCL Technologies/Wipro
5. KPIT Cummins Infosystems
5. Mphasis/BFL
6. Symphony
7. Sonata Software
8. Mistral/eInfochips
9. Dexcel Designs
10. Robosoft/Yindusoft

Yes, do feel free to disagree, friends! :) Again, I know this may not be a perfect list!
There are several companies in the embedded space within India who have been really doing outstanding work. I will try my best to contact as many of these companies and find out what these folks are presently working on!

I will also TRY and revise this list, IF I am able to round up as many companies, and am able to rank them, based on the solidity of their current projects, and NOT on the revenue gained in 2008. Again, I agree, this criteria may not appeal to all, but then it is my list :)
Therefore, feel free to disagree, folks… and please add several names of these great Indian companies in the embedded systems and software space, along with their email IDs, so I can easily touch base with them!

PS: One reader has mentioned about whether these companies have great products! Well, would be great if the companies could come up and say how great their products are!!
Thanks for the feedback, Mr. Nair, and good to have new names… :)

Another reader had mentioned ProcSys! Many thanks for those names, friends!

Sofcon India Pvt Ltd

Sofcon affiliate & Funded By NSDC approved Embedded Systems Engineering Training Institute in India and avilable in various cities.

1. Embedded Training in Noida

2. Embedded Training in Delhi

3. Embedded Training in Gurgaon

4. Embedded Training in Ghaziabad

5. Embedded Training in Lucknow

6. Embedded Training in Bhopal

7. Embedded Training in Baroda

8. Embedded Training in Rajkot

9. Embedded Training in Ahmedabad

10.  Embedded Training in Jaipur

Reliance Industries Use PLC Scada Technologies

Reliance Industries Ltd (RIL) had shared all the copies of its correspondence with the Supreme Court-appointed tribunal on the KG-D6 cost recovery issue to the Oil Ministry and the Directorate General of Hydrocarbons (DGH), according to sources.

Contrary to the impression being created, RIL had, subsequent to Supreme Court on April 29 appointing former Australian judge Michael Hudsom McHugh as third arbitrator to decide whether government was right in denying cost recovery of up to $2.3 billion for gas output from KG-D6 lagging targets, marked all correspondence-related mails with the tribunal to the ministry and the DGH, they said.

Mr McHugh had on May 20 declined to be part of the tribunal saying his consent was not taken, but subsequently agreed after lawyers for RIL and its partners BP Plc of the UK and Canada's Niko Resources contacted him on May 29.

Sources said RIL's advocates in an email on May 29 requested Mr McHugh to accept his appointment as the third/presiding arbitrator of the tribunal. A copy of Tom Sprange's (RIL's lawyer) email was marked to the Oil Ministry and its technical arm, Director General of Hydrocarbons (DGH).

Government lawyers Swarup & Associates, who have now told the ministry that appointment of a foreigner as the presiding arbiter would be "undesirable" in the absence of any such contractual provision and difficulty in ascertaining the person's "independence and impartiality", was not marked on the email as it was not known at that time who would act for the government of India, they said.
Thereafter emails and correspondence were exchanged between the RIL and the Tribunal with respect to the fixing of fee for the arbitrators. By this time, government lawyers were intimated and they were marked on those emails but they chose not to reply, sources said.

On June 18, RIL's lawyers sent a letter to government's advocate stating copies of all the correspondence between the arbitrators and the parties will be provided to them.

Mr McHugh on June 26 sent an email to all the parties on behalf of all arbitrators enclosing a working draft procedural timetable but a week later on July 2 government advocates sent emails asking the tribunal not to proceed with the matter till a detailed response is issued by them and asked the tribunal to send copies of all the documents correspondence exchanged.

Sources said the government felt Mr McHugh appointment stood terminated the moment he declined to accept the appointment and thereafter he cannot reappoint himself.

Mr McHugh withdrew from the tribunal and RIL filed a fresh plea before the Supreme Court for appointment of a third arbitrator to decide on the case.

Sofcon India Pvt Ltd

Sofcon is group of companies since 1995. We are affiliate & funded by NSDC and Sofcon provide PLC Training in Noida and PLC Training in Delhi.



Source:-http://profit.ndtv.com/news/corporates/article-reliance-industries-shared-all-correspondence-with-oil-ministry-technical-arm-report-619675

PLC Numerical Systems

Numerical systems

 INTRODUCTION

 D.1 Decimal numerical system

 D.2 Binary numerical system

 D.3 Hexadecimal numerical system

Introduction

People were always difficult to except the fact that something is different from themselves or their way of thinking. It is probably one of the reasons why numerical systems other than decimal are hard to understand. Still, whether we like it or not, reality is quite different. Decimal system used in everyday life is by far less used than binary code, which is the working basis for millions of computers across the world.

Each numerical system rests upon its basis. With decimal numerical system, this basis is 10, with binary it is 2, while with hexadecimal it equals 16. Value of each digit depends on it’s position in the number, represented in certain numerical system. Sum of values of each digit is the value of the number. Binary and hexadecimal systems are especially interesting for this course. Besides these two, decimal system will be detailed, too, for the sake of comparison. Although there is nothing new to tell about decimal system, we will give it a look for its relations with other numerical systems.

D.1 Decimal numerical system

Decimal numerical system is defined with its basis 10 and decimal positioning from right to left, and it consists of digits 0,1,2,3,4,5,6,7,8,9. This means that the rightmost digit is multiplied by 1 in total sum, next digit to it is multiplied by 10, next one by 100, etc.

Example:

Operations of addition, subtraction, division and multiplication in decimal numerical system are well known, so we will not detail these.
 D.2 Binary numerical system

Binary numerical system is quite different from the decimal that we got used to in common life. Its basis is 2 and each digit can have one of two values, “1” or “0”. Binary numerical system is used for computers and microcontrollers, because it is much easier for processing than decimal. Usually, binary number consists of 8, 16 or 32 binary digits. Origins of this division are irrelevant for this course, so we will just take it for granted.

Example:
10011011 - binary number with 8 digits

To understand the logic of binary numbers, let us have an example. Let’s assume that we have a cabinet with four drawers and that we should tell someone to bring us something from one of these. Nothing simpler, we could say “in the lower row on the left” and it would be quite sufficient. However, if it must be done without this kind of orientation, left, right, up, down and the likes, then we have a problem. There is a plenty of solutions for the situation, but we should look for the best and the most efficient! Let us mark the columns with A and rows with B. If A=1, we assume the upper row of drawers, and if A=0 we assume the lower. Similar with columns, B=1 is the left column and B=0 is the right column (following picture). Now, it is easier to explain which drawer we think of, just use one of the four combinations 00, 01, 10 or 11. This “naming” of each drawer is nothing more than binary nomenclature of numbers, that is, converting decimal numbers into binary system. In short, labels “first, second, third and fourth” are substituted with “00, 01, 10 and 11”.

We still need to understand the logic of binary numerical system, i.e. how to get the decimal value of a number out of the sequence consisting of ones and zeros. This procedure is called conversion of binary number to decimal value.

As it can be seen, conversion of binary number to decimal value is done by totaling the sum on the right. Depending on the position in the binary number, digits carry different “weight” multiplied by themselves, and totaling them all gives us an understandable decimal number.

Let’s further assume that there are marbles in each of the drawers, 2 in the first, 4 in the second, 7 in the third and 3 in the fourth. Let the person opening the drawers also use the binary system. Under these conditions, question would be “How many marbles are there in 01?”, and the answer would be “There are 100 marbles in 01!” Notice that both question and answer are clear, although we did not use common terminology. Further, notice that two digits are sufficient for decimal numbers from 0 to 3, and that all values greater than 3 require additional binary digits. Thus, for 0 ~ 7 range, three digits are sufficient, four digits cover the range 0 ~ 15, etc. Simply put, the greatest decimal number that can be represented with n binary digits is 2 raised to power n, decreased by one.

Example:
2⁴-1 = 16 - 1 = 15

So, 4 binary digits cover decimal values from 0 to 15, including the values “0” and “15”, which is 16 different values. 

Arithmetical operations that exist in decimal numerical system also apply in binary system. In this chapter, we will cover only addition and subtraction, for simplicity sake.

Basic rules that apply to binary addition are:
Addition works similar to decimal numerical system - we add the digits of the same weight. If both digits added are zero, the result remains zero, while “0” and “1” total “1”. Two ones give zero, but one is carried to the left position.

We can do the check by converting these numbers to decimal system and adding them. Value of the first number is 10, value of the second is 9 and 19 as result, which means that operation was done correctly. Problem occurs when the result is greater than can be represented with given number of binary digits. There are various solutions, one of them being expanding the number of binary digits like in the example below.
 

Subtraction works on the same principles as addition does. Two zeros give zero in result, as do two ones, while subtraction of one from zero requires borrowing one from the higher position in binary number. Example:
Conversion of numbers to decimal system gives as values 10 and 9, with the result of subtraction of 1, which is correct.

D.3 Hexadecimal numerical system

Hexadecimal numerical system has number 16 for basis. Therefore, there are 16 different digits used in this system. These are “0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F”. Letters A, B, C, D, E and F represent values 10, 11, 12, 13, 14, 15 and are used for the sake of easier notation. As with binary numerical system, we can apply the same formula here for determining the greatest decimal number that can be represented with a given number of hexadecimal digits.


Example:
16² - 1 = 256 - 1 = 255

Usually, hexadecimal numbers have prefix “$” or “0x” to emphasize the fact that hexadecimal system is used. Thus, number A37E should be represented with $A37E or 0xA37E. No calculations are needed for converting the hexadecimal number to binary system - it is simple substituting of hexadecimal digits with binary ones. Since maximum value of hexadecimal digit is 15, 4 binary digits are required per one hexadecimal.
 

Example:
Check, i.e. converting both numbers to decimal system, gives us value 228 which is correct.

In order to calculate decimal equivalent of hexadecimal number, each digit of number should be multiplied by 16 raised to power equal to the position in the number and then added altogether.

Addition works similar to two previous numerical systems.

Example:
It is required to add the appropriate digits of a number, and if their sum equals 16, that position takes value “0”. Values exceeding 16 should be added to the sum of digits on higher position. First number converted equals 14891, while other is 43457. Their sum is 58348, that is $E3EC converted to decimal numerical system. Subtraction works identically to previously mentioned systems.

Example:
Conversion gives us numbers 11590 and 5970, and the result of subtractions is 5620, that is $15F4 converted to decimal numerical system.

Conclusion

Binary numerical system remains the most commonly used, decimal system the most intelligible, while hexadecimal is somewhere in between. It’s simple conversion to binary system makes it, besides binary and decimal, the most important numerical system to us.

PLC Diagnostics

PLC diagnostics

 INTRODUCTION

 C.1 Diagnostic functions of PLC

 C.2 Non-fatal errors

 C.3 Fatal errors

 C.4 User defined errors

 C.5 Failure alarm - FAL(06)

 C.6 Severe Failure alarm - FALS(07)

 C.7 MESSAGE - MSG(46)

 C.8 Syntax errors

 C.9 Algorithm for finding errors in the program

Introduction

The whole work of PLC controller can be represented with a diagram shown on the following page. After turning on the power, PLC is first initialized (clearing IR, SR i AR areas, presetting system timers and checking I/O lines), and if no errors were detected, monitoring process, program execution, calling the I/O lines and serving the peripheral devices starts to occur in cycles.

C.1 Diagnostic functions of PLC

PLC controller features additional functions that make locating errors easier. Errors can be divided into two categories according to severity :

1. Fatal errors are severe and they prevent PLC controller from operating until their cause is located and solved.
2. Non-fatal errors are those that do not prevent PLC controller from operating. After detecting one or more non-fatal errors, program execution will continue. Nevertheless, it is necessary to correct these errors as soon as possible.

C.2 Non-fatal errors

When one of these errors takes place, indicators POWER and RUN will be on, and the indicator ERR/ALM will blink. Upon locating non-fatal error, manual for the given PLC controller should be consulted and the flags checked in order to understand the cause of a problem and correct the error.

C.3 Fatal erros

When any of the fatal errors take place, PLC controller stops operating and all outputs are shut down. PLC controller cannot be put back to work until the controller is turned off and then turned back on, or until it is switched to PROGRAM mode via peripheral device and the fatal error corrected. With these errors, indicators ERR/ALM are on, while the RUN indicator remains off. It is necessary to check the error flag in the manual of the given PLC in order to locate the cause of the problem and to correct the error.

C.4 User defined errors

There are three instructions for user to define his own errors or messages. FAL(06) causes non-fatal error, FAL(07) causes fatal error, while MSG(46) sends a message to program console or to the host computer connected to the PLC controller.
 

C.5 Failure alarm - FAL(06)

Instruction FAL(06) generates the code of non-fatal error that took place to provide the information on the possible cause of the problem for the programmer. Upon execution of the instruction FAL(06) following events take place:

1. Indicator ERR/ALM will blink, while PLC continues to work.
2. Two-digits BCD number of instruction FAL (01 do 99) is written from SR253000 to SR25307.

Same number must not be assigned to both FAL and FALS instructions. To delete the code of an error, error should be corrected and FAL 00 instruction executed.

C.6 Severe failure alarm - FALS(07)

Instruction FALS(07) generates the code of fatal error that took place. In this case the following happens:

1. Program stops and all outputs are shut down.
2. Indicator ERR/ALM is turned on.
3. Two-digit BCD number (01 do 99) of instruction FALS is written from SR 253000 to SR25307.
4. If memory card with RTC is used, part of the memory where the presence of error is recorded will also contain numbers of FALS instruction and exact time when error took place.

Numbers of FALS instruction can be assigned to certain states. Same number must not be assigned to both FAL and FALS instructions. To delete FALS error, PLC controller must be in PROGRAM mode, cause of error solved and then error code deleted.

C.7 Message - MSG (46)

MSG(46) is used for printing messages on program console display. Message cannot exceed 16 characters, and it appears when specified condition is fulfilled.

C.8 Syntax errors

During the program check with operation Program Check, syntax errors are detected. There are three levels of program check at user’s disposal. By selecting the level, types of errors to be checked for are selected. The following table shows types of errors, corresponding messages that appear on display and explains all of syntax errors. Zero level check searches for errors of A, B and C type. First level check searches for errors of A and B type, while the second searches only for errors of type A.

Type	Message	Meaning and the appropriate action
A	?????	Program is damaged by creating non-existing function in the code. Re-enter your program.
	CIRCUIT ERR	Number of logical blocks doesn't match the instructions of logical blocks. Check the program.
	OPERAND ERR	Entered constant is not in allowed range. Change the constant so that it fits in the proper range.
	NO END INSTR	Program is missing the instruction END(01). Add END(01) to the last address of the program.
	LOCN ERR	Instruction is in the wrong place of the program. Check what the instruction demands and correct the mistake.
	JME UNDEFD	Instruction JME(04) is missing the instruction JMP(05). Correct the number of jump and add the correct JME(04) instruction.
	DUPL	Same number of jump or subroutine is used twice in the program. Correct the program so that each number is used only once.
	SBN UNDEFD	Instruction SBS(091) is programmed for non-existing subroutine. Correct the number of subroutine or create the missing one.
	STEP ERR	STEP(08) with the number of section and STEP(08) without the number of section are used illegally. Check the demands of instruction STEP(08) and correct the mistake.
B	IL-ILC-ERR	IL(02) and ILC(03) are not used in pair. Check if every instruction IL(02) has its corresponding ILC(03). This message will also appear in case that multiple IL(02) instructions were used with single ILC(03) instruction. Check if that's exactly what you wanted...
	JMP=JME ERR	JMP(04) and JME(05) are not used in pair. Before proceeding, check if the program is written exactly the way you wanted.
	SEN-RET ERR	If the address of instruction SBN(92) is displayed, there are two different subroutines with the same number. Change one of the numbers or delete one of the subroutines in question. If the address of instruction RET(93) is displayed, RET(93) wasn't used appropriately. Check the demands of this instruction and correct the mistake.
C	COIL DUPL	Same bit is controlled by more than one instruction (for example, OUT, OUT NOT, DIFU(13), KEEP(11), SFT(10)...). Although certain instructions allow this, you should check the demands of specific instructions, make sure that the program is correct or rearrange the program so that each bit is controlled by single instruction.
	JMP UNDEFD	JME(05) is used without JMP(04) with the same number of jump. Add the instruction JMP(04) with the same number or delete JME(05) that is not used.
	SBS UNDEFD	There is a subroutine that is not called by SBS(91). Add subroutine call to an appropriate place in the program or delete the subroutine.

C.9 Algorithm for finding errors in the program