Greater Integration Between the SCADA and DMS

Moves towards a smarter grid are seen in the form of greater integration between the SCADA and DMS throughout the transmission network and medium-voltage equipment. Moreover, as utilities roll-out Advanced Metering Infrastructure (AMI), the integration of AMI data with the DMS is a defining aspect of the smart grid. The integration of AMI data with DMS applications is expected to deliver benefits such as shorter outage duration, better management of system loading, and improved voltage profiles. From the customer’s perspective, smart meters are intended to increase awareness of energy usage, including real-time and historical information, which should help reduce overall energy consumption. This simplifies network-management challenges for utility companies, while empowering consumers to reduce their own energy bills.

Smartening the distribution network

A growing number of smart devices are being installed in substations and distribution systems. These include intelligent controls for voltage regulators used for volt/VAR control, and line reclosers and switches used for tasks such as automatic switching, fault isolation, and automatic restoration after temporary faults.

The use of serial communication protocols for communicating with intelligent controllers, or integrated devices such as smart reclosers, is giving way to Ethernet-based networking using the latest IEC 61850 communication standard. In addition to promoting interoperability and eliminating protocol diversity, IEC 61850 incorporates the GOOSE (Generic Object Oriented Substation Events) protection-speed messaging protocol, which enables high-speed protection, transfer switching, fault isolation, and service restoration. The high speed of the GOOSE protocol allows intelligent controllers or smart reclosers communicating on a peer-to-peer basis to identify the location of a fault, and therefore avoid the voltage disturbances caused by repeated actuation of conventional reclosers. When the fault is pinpointed, the operator can take the correct remedial action to restore service and repair the fault.

To implement comprehensive measurement, protection and automation functionalities at the recloser level, multiple voltage sensors and current transformers are required. Current transformers are used to measure the current in each phase accurately. CR Magnetics has a range of commercial and metering-class current transformers, which can be used for various monitoring and fault-detection duties and includes devices rated up to 4000 A. The metering-class transformers provide high accuracy and minimum phase-angle error. Current transformers allow non-contact monitoring of the current in a conductor by passing the conductor through the transformer’s central window. The CR Magnetics range features square and circular current transformers including the CR7310, which can be used for detecting ground faults or other causes of 3-phase imbalance. All three phases and neutrals are routed through the transformer window, and the sum of the 3-phase Y currents is expected to be zero when the loads are equal. If there is an imbalance, the phases do not cancel and the relay trips.

Smart meters reach the customer

While IEC 61850 communication over Ethernet is becoming more widely used at the substation and feeder level, power line communication (PLC) using a protocol such as IEC 61334, PRIME (PoweRline Intelligent Metering Evolution), or G3-PLC enables utilities to leverage their existing power line infrastructure to communicate with smart meters installed at customer premises. Low-frequency narrowband PLC is typically used, at frequencies up to 500 kHz.

The underlying functional elements of a smart meter, which comprise analog measurement, processing and communications, may be implemented using discrete Analog Front-End (AFE), processor and communication modem components, or using a more integrated approach.

Texas Instruments’ TMS320F28 PLC microcontroller seeks to simplify design while preserving flexibility by integrating the PLC modem functionality and providing a development platform including a PLC modem hardware-configuration tool and the plcSUITE™ software framework. This platform allows developers to quickly develop and test robust PLC implementations and provides flexibility to separate the modulation implementation, the protocol design, and the development of the application. The platform provides a graphical user interface that helps developers visualize and fine-tune key PLC modem performance parameters. Combined, this modular hardware architecture and flexible software framework creates the industry’s only PLC technology capable of supporting multiple standards and modulation schemes with a single platform. Developers can use this platform to create a variety of PLC solutions for smart-energy applications, as shown in Figure 2, with the flexibility to adapt as the applicable standards evolve.

Figure 2: PLC technology is ideal for a wide range of smart-energy devices for consumer, municipal, and transmission applications.

STMicroelectronics has combined processing functionality, PLC modem, and analog front-end into a single System-on-Chip (SoC) device in its STarGRID family of PLC SoCs. As Figure 3 illustrates, the STarGRID platform includes an 8051 processor core for protocol control duties, combined with a separate DSP, giving the flexibility to support multiple modulation schemes. The power line driver, analog front-end, and auxiliary functions such as power and clock management are also integrated. The family of devices includes the ST7580, which is currently being used in 13 million smart meters by the utility companies ENEL and ENDESA, which have operations in southern Europe and Latin America. A similar device, the ST7590, is certified by the PRIME Alliance and used by the Spanish energy group Iberdrola in the 11 million meters deployed as part of its STAR project.

Figure 3: Key functional elements of the STarGRID® narrowband SoC platform.

Controlling the new functionality

The design of today’s electronic smart meters takes advantage of remote communications, via PLC or wireless, to implement features and capabilities that have not been possible with traditional electromechanical meters. Among these is the service-disconnect switch, which is used to disconnect a property from the grid for safety reasons such as if the premises are unoccupied or during maintenance or emergencies. By integrating this function as an electronically-controlled switch in the smart meter, it can be actuated from a remote location. This not only allows safety or emergency disconnect instructions to be carried out quickly and efficiently, but also gives utility companies extra flexibility to manage demand and maintain grid stability and voltage levels. The switch is typically a dual-coil polarized latching relay, which requires no holding current to maintain the contacts in either an open or closed state. To ensure reliable delivery of relay-control pulses generated by the microcontroller, and minimize the possibility of tampering, a suitable relay driver such as the Fairchild Semiconductor FAN324x may be used. The FAN3240 has outputs rated for operation from 8 V to 60 V, and integrates a filter/timer block that prevents inadvertent switching from noisy input signals.

Conclusion

The transition to a smart grid is an ongoing process that applies to the entire electricity transmission and distribution network, and has already been taking place for some time. Distribution companies have been using data from SCADA in progressively smarter ways, and driving SCADA further into the network in pursuit of the same goals that are associated with the smart grid as it is understood today. Smart meters capable of providing richer data both to utilities and consumers, represent the final link, bringing smart technology into customers’ premises and general public awareness.

http://www.digikey.com/en/articles/techzone/2013/nov/keeping-the-smart-grid-smart

Achieving Better Embedded Software Performance Through Memory Layout Optimization

Software Engineering for Embedded Systems, Mike Brogioli of Polymathic Consulting provides tips on various memory layout optimization techniques that can be used to improve embedded system performance.

In order to obtain sufficient levels of performance, application developers and software systems architects must not only select the appropriate algorithms to use in their applications, but also the means by which those applications are implemented. Quite often this also crosses the line into data structure design, layout and memory partitioning for optimal system performance.

It is true that senior developers often have insight into both algorithms and their complexity, as well as a toolbox of tips and tricks for memory optimization and data structure optimization. At the same time, the scope of most embedded software engineering projects prohibits manual code and data hand optimization due to time, resource and cost constraints.

As such, developers must often rely on the tools as much as possible to optimize the general use cases, only resorting to hand-level tuning and analysis to tweak performance on those performance-critical bottlenecks after the initial round of development.

This last round of optimization often entails using various system profiling metrics to determine performance-critical bottlenecks, and then optimizing these portions of the application by hand using proprietary intrinsics or assembly code, and in some cases rewriting performance-critical kernel algorithms and/or related data structures. This article follows on from the topics discussed in Part 1 and details design decisions that may prove useful for embedded system developers concerned with the issues those topics mentioned above.

Overview of memory optimization
Memory optimizations of various types are often beneficial to the run-time performance and even power consumption of a given embedded application. As was mentioned previously, these optimizations can often be performed to varying degrees by the application build tools such as compilers, assemblers, linkers, profilers and so forth. Alternatively, it is often valuable for developers to go into the application and either manually tune the performance or design in consideration of memory system optimization a priori, for either given performance targets or so as to design the software architecture to be amenable to automated-tool optimization in subsequent phases of the development cycle.

In tuning a given application, quite often the baseline or “out of box” version of the application will be developed. Once functionality is brought online, the development team or engineers may select to profile the application for bottlenecks that require further optimization. Often these are known without profiling, if certain kernels within the application must execute within a given number of clock cycles as determined by a spreadsheet or pen and paper exercise during system definition. Once these key kernels are isolated or key data structures are isolated, optimization typically begins by those experts with knowledge of both software optimization techniques, compiler optimizations, the hardware target and perhaps details of the hardware target instruction set.

Focusing optimization efforts
Amdahl’s law plays an interesting role in the optimization of full application stacks, however, and is not always appreciated by the software system developer. If only 10% of the dynamic run-time of a given application can benefit from SIMD or instruction-level parallel optimizations versus the 90% of dynamic run-time that must be executed sequentially, then inordinate amounts of effort on parallelizing the 10% portion of the code will still only result in modest performance improvements. Conversely, if 90% of the total application’s dynamic run-time is spent in code regions exhibiting large amounts of instruction-level parallelism and data-level parallelism, it may be worthwhile to focus engineering effort on parallelizing these regions to obtain improved dynamic run-time performance.

In determining those portions of the code which dominate the dynamic application run- time, and may be the best candidates for either hand optimization or hand adjustment for applicability to automated-tool optimization, application developers typically use a software profiler in conjunction with either the silicon target or software-based system simulation. Intel’s VTUNE is one such example of a profiling framework; alternatively the GNU GCC compiler and GPROF are open-source solutions that provide dynamic run-time information. Many silicon vendors such as Freescale Semiconductor and Texas Instruments also offer their own proprietary solutions for use with their respective silicon targets, allowing for either traces collected on software-based simulation platforms, or alternatively larger application-level traces that can be collected on the native silicon target.

Vectorization and the dynamic code: compute ratio
Vectorization of loops is an optimization whereby computation performed across multiple loop iterations can be combined into single vector instructions, effectively increasing the instruction-to-compute ratio within the application’s dynamic run-time behavior. Consider the example in Figure 5.

     short a[16], b[16], c[16];
     for(iter=0; iter<16; ++iter)
     {
          // results in single 16-bit MPY instruction
          // generated in assembly listing
          //
          a[iter] = b[iter] * c[iter]
     }

     short a[16], b[16], c[16]; for(iter=0; iter<16 iter+=4)
     {
          // with high level compiler vectorization,
          // results in 4-WAY parallel 4x16-BIT multiply
          // vector instruction, effectively performing the
          // computation of four iterations of the loop in
          // a single atomic SIMD4 instruction.
          //
          a[iter:iter+4] = b[iter:iter+4] * c[iter:iter+4];
     }

Figure 5: Loop level vectorization example

In the first loop nest, we can see that each iteration of the loop contains a single 16-bit by 16-bit multiply instruction whose result is written to the a[] array as output. One multiplication instruction is performed for each iteration of the loop, resulting in 16 16-bit multiplications. The second loop, however, shows pseudocode for how the compiler or application developer might vectorize the loop when targeting an architecture that supports a four-way SIMD multiply instruction over 16-bit integer elements.

In this case, the compiler has vectorized multiple iterations of the loop together into the multiply instruction, as denoted by the array[start_range:end_range] syntax denoted in the second loop nest. Note that the loop counter is incremented by the vectorized length for each iteration of the loop now. Clearly only four iterations over the loop are now needed to compute the resulting an output array, as each iteration of the loop now contains a single vector multiply instruction that computes four elements of the output vector in parallel.

There are many benefits to vectorizing code in this manner, either by hand if the application developer uses intrinsics that are proprietary with respect to the target architecture, or if the compiler is able to vectorize the code. One such benefit is the increase in performance, as the code now exploits dedicated SIMD hardware, often providing a multiplication in improvement over the vectorized loop on the order of the underlying SIMD vector hardware.

Other benefits are the reduction in code size, as loops are no longer unrolled resulting in explosions in the code size, but rather more dense instructions of vector format are used rather than atomic scalar instructions. This may have secondary benefits in reducing the number of instruction fetch transactions that go out to memory as well. Lastly, the overall ratio of dynamically issued instructions to computation performed within the application is increased as well.

There are a number of challenges to both the development tools and the application developers when trying to vectorize code at the loop level. One such challenge is the code shape of loop nests that are candidate for vectorization. Typically, build tools need to understand the loop iteration space of a loop, so using constant loop bounds rather than run- time computed values may be beneficial depending on the advancement of the underlying compiler’s vectorization technology.

Secondly, the types of computation performed within the loop nest must be amenable to vectorization. For example, in the example above simple 16-bit integer multiplication is performed for a target architecture supporting a supposed 16-bit four-way SIMD multiply instruction. If the underlying target architecture only supports 8-bit SIMD multiplication, it may be advantageous to avoid 16-bit multiplication wherever possible if vectorization is desired.

Loop dependence analysis is another concern when vectorizing or parallelizing loop nests, as the compiler must be able to prove the safety of loop transformations. Loop dependence analysis is the means by which the compiler or dependence analyzer determines whether statements within a loop body form a dependence with respect to array accesses and data modifications, various data reduction patterns, simplification of loop-independent portions of the code and management of various conditional execution statements within the loop body.

As an example, consider the fragment of C-language code in Figure 6.

     for(iter_a=0; iter<LOOP_BOUND_A; ++iter_b)
        for(iter_b=0; iter_b<LOOP_BOUND_B; ++iter_b)
           a[iter_a+4-iter_b] =
              b[2*iter_a-iter_b]+ iter_a*iter_b;

Figure 6: Fragment of C language code

For the loop above, the compiler’s data dependence analyzer will attempt to find all dependences between the statements reading the array b[] and writing to the array a[]. The challenge for the data dependence analyzer is to find all possible dependences between the statements that write to array a[] and read from array b[]. To ensure safety, the data dependence analyzer must ensure that it can explicitly prove safety or, in other words, any dependence that cannot be proven false must be assumed to be true to ensure safety!

The data dependence analysis shows independence between references by proving that no two instances of statements to array a[] and array b[] access or modify the same spot in array a[]. In the event that a possible dependence is found, loop dependence analysis will make an attempt to characterize the dependences, as some types of optimizations over loop nests may still be possible and profitable. It may also be possible to further transform the loop nests so as to remove the dependence.

In summary, writing loop nests so that a minimum of data dependencies exists between array references will benefit vectorization and other loop transforms as much as possible. While the compiler technology used in analyzing data dependencies and autovectorizing serial code for vector hardware stems from the supercomputing community, improperly written code with troublesome data dependencies and loop structure may still thwart the vectorization efforts of the most advanced tool sets.

At a high level, simply writing code which is easiest for humans to understand usually produces code that is easiest for the vectorizer to understand as well, as the vectorizer and data dependence analyzers can easily recognize what the programmer intended. In other words, highly hand-tuned code with a priori knowledge of the underlying target architecture is not the best candidate for automated vectorization at the tools level.

There are a number of things that application developers may want to keep an eye out for when developing code with the intent of autovectorization by the build tools.

Pointer aliasing in C
One challenge for vectorizers and data dependence analysis is the user of pointers in the C language. When data is passed to a function via pointers as parameters, it is often difficult or impossible for the data dependence analyzer and subsequent vectorizer to guarantee that the memory regions pointed to by the various pointers do not overlap in the interaction spaces of the loops in which they are computed. As the C standard has evolved over time, support for the “restrict” keyword has been added, as can be seen in the example in Figure 7.

     void restrict_compute(restrict int *a, restrict int
     *b, restrict int *c)
     {
          for(int i=0; i<LIMIT; ++i)
               a[i] = b[i] * c[i];
     }

Figure 7: C Standard “restrict” keyword

By placing the restrict keyword qualifier on the pointers passed to the procedure, this ensures to the compiler that the data accessed by a given pointer with the restrict keyword does not alias with anything else the function may modify using another pointer. Note that this only applies to the function at hand, not the global scope of the application itself. This permits the data dependence analyzer to recognize that arrays are not aliased or modified by references with other side effects, and allows more aggressive optimization of the loop nest including vectorization amongst other optimizations.

Source:-http://www.embedded.com/design/debug-and-optimization/4436459/Achieving-better-embedded-software-performance-through-memory-layout-optimization-Part-2                        

Sensor Fusion Goes Open-Source

AUSTIN, Texas – Analog Devices, Freescale, PNI Sensor Corp., and the MEMS Industry Group formed the Accelerated Innovation Community, a group dedicated to providing open-source algorithms for sensors. AIC also plans to announce an I/O standard for sensors in collaboration with the MIPI Alliance.

Engineers shouldn't have "to reinvent the wheel on common algorithms every time they want to add or change functionality in their product," said Karen Lightman, executive director of the MEMS Industry Group (MIG). "Access to an open-source library of introductory algorithms fundamentally changes the development paradigm."

Freescale was an early catalyst of AIC and has added open-source algorithms such as a C source library for 3-, 6- and 9-axis sensor fusion. Sensor fusion is a basic building block for sensor data analytics and for motion tracking, said Freescale's Ian Chen.

"It's all about bringing the relevant data together from multiple sensors to provide a bigger picture of what's going on in a system," Steve Whalley, chief strategy officer at MIG and a former director of sensors at Intel, told EE Times. AIC aims to let engineers "focus their own real differentiating capabilities on the more complex algorithms that are needed for today's products above and beyond the introductory algorithms in the AIC."

Steve Whalley

The key challenge in sensor fusion is effectively separating signal, motion, and noise, Chen said. AIC's algorithms aim to take redundant data from different sensors that observe the same event to distinguish between noise and signals, then compute more accurate information.

"Sensor fusion encompasses a variety of techniques which leverage the inherent strengths and monitoring that these individual sensors do to achieve more accurate results than the individual components could achieve by themselves," Chen told EE Times.

Source:-http://www.eetimes.com/document.asp?doc_id=1324503&

Synopsys Simplifies Low Power Lot Sensor & Controller Soc Design

Synopsys, Inc. has just released a complete hardware and software IP building block optimized for a wide range of ultra-low power embedded sensor and control applications.


"Embedded sensor and control applications require a high level of integration with minimal power and area," said John Koeter, vice president of marketing for IP and Prototyping at Synopsys.

To achieve this goal, he said, the company's Sensor and Control IP Subsystem integrates the DesignWare ARC EM4, EM6, EM5D or EM7D 32-bit processors, delivering efficient real-time control and DSP performance required for ultra-low power sensor- and control-based applications.
Newly integrated peripherals include a UART for serial communication as well as a Pulse Width Modulation (PWM) block and Digital-to-Analog Converter (DAC) interface for actuator/motor control functions.

An optional IEEE 754-2008 compliant floating point unit (FPU) reduces energy consumption by up to 10X for sensor fusion applications implementing floating point operations. He said designers using the DesignWare building block are provided with a pre-verified, SoC-ready IP subsystem that delivers the energy- efficient processing required in markets such as the Internet of Things (IoT).
Koeter said the subsystem is designed to process data from digital and analog sensors and always-on audio sources with minimal power consumption. "This enables offloading of the host processor and more efficient processing of the data,

" he said.
The fully configurable subsystem includes the choice of an ARC EM4, EM6, EM5D or EM7D processor. All the processors support up to 2 MB of closely coupled memory (CCM) for both instruction and data, while the EM6 and EM7D also incorporate up to 32 KB of instruction and data cache for maximum system performance and flexibility.

The EM5D and EM7D provide developers with a high-efficiency control and signal processing capability that gives them access to more than 100 DSP instructions. Included in the subsystem are integrated UART, PWM and ARM AMBA APB interface peripherals combined with the configurable GPIO, SPI, I2C and ADC/DAC interfaces for a variety of off-chip sensor and actuator connections.

Targeted at designs where it is necessary to process the extensive amount of data in sensor fusion applications, the subsystem includes a rich library of off-the-shelf DSP functions supporting filtering, correlation, matrix/vector, decimation/ interpolation and complex math operations.

"Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP instructions within the EM5D or EM7D processor and tightly coupled hardware accelerators," said Koeter, "to boost performance efficiency and reduce power consumption by up to 85 percent compared to discrete solutions. "

An optional IEEE 754-2008 compliant FPU reduces energy consumption by up to 10X for sensor applications requiring single- or double-precision floating point operations. Additionally, the ARC Processor EXtension (APEX) technology enables designers to add their own user-defined instructions or existing hardware to the processor. 

ICS-CERT warns BlackEnergy malware attacking SCADA system HMI

The US Department of Homeland Security's Industrial Control System Cyber Emergency Response Team (ICS-CERT) has just issued an alert about malware that is targeting human-machine interfaces (HMIs) of industrial control systems. https://ics-cert.us-cert.gov/alerts/ICS-ALERT-14-281-01A.


It is based on a varient BlackEnergy malware toolkit malware that infects HMIs on any supervisory control and data acquisition system (SCADA) that has a direct connection to the Internet. It is a continuation of a malware campaign targeting numerous companies that has been ongoing since 2012.

In applications where an ability to remotely monitor or operate the system is required, the SCADA/HMI is often connected to the public Internet as the link to the remote operator. It is such installations that the BlackEnergy malware has been attacking the alert warns.

So far, the report lists three commercial SCADA/HMI software products are listed in ICS-ALERT-14- 281-01A, including GE Cimplicity, Advantech/Broadwin WebAccess, and Siemens WinCC for SIMATIC.

The ICS-CERT analysis indicates the attack involves making an HMI server run a malicious screen file hosted on an attacker-controlled server, which then installs the malware. According to the alert "at this time, ICS-CERT has not identified any attempts to damage, modify, or otherwise disrupt the victim systems’ control processes."

Howver, ICS-CERT warns that this kind of malware usually searches for removable media and network-connected file shares that can provide a pathway into the target company's computer networks.

Source:http://www.embedded.com/electronics-news/4436970/ICS-CERT-warns-BlackEnergy-malware-attacking-SCADA-system-HMIs

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Research and Markets: Industrial Automation Control (DCS, PLC, MES, APC & SCADA) Market in the Americas 2014-2018

Web-based automation solutions provide complete real-time information from production plants, which increases the production process. A web-based automation solution integrates with various production plants at the shop floor level and shares the information gathered through a common database. Thus, it helps improve the decision-making system and reduces the total cost of ownership. Therefore, the cost-effectiveness of this solution is expected to enhance the demand for web-based automation solutions in many cost-sensitive industries.

According to the report, the need to improve the decision-making process across industries is one such driver. Real-time delivery of accurate operational information offered by industrial automation solutions aids the decision-making process of plant engineers.

Further, the report states that an automation solution requires significant investment, not only for installation, but also for regular upgrades, and integration and support. Therefore, the overall cost of adopting these solutions is very high.

The study was conducted using an objective combination of primary and secondary information including inputs from key participants in the industry. The report contains a comprehensive market and vendor landscape in addition to a SWOT analysis of the key vendors.
Industrial automation systems include five major types:

• DCS
• PLC
• MES
• APC
• SCADA.

Key Vendors

• ABB Ltd.
• Honeywell International Inc.
• Rockwell Automation Inc.
• Siemens AG

Other Prominent Vendors

• Applied Material Inc.
• Apriso Corp.
• Aspen Technologies Inc.
• Camstar Systems Inc.
• Control Systems International Inc.
• Emerson Electric Co.
• Eyelite Inc.
• GE Co.
• Invensys plc
• Metso Corp.
• Miracom Inc.
• Mitsubishi Heavy Industries Ltd.
• Omron Corp.
• SAP AG
• Schneider Electric SA
• Toshiba International Corp.
• Werum Software & Systems AG
• Yokogawa Electric Corp.

Key Topics Covered:

1. Executive Summary
2. List of Abbreviations
3. Scope of the Report
4. Market Research Methodology
5. Introduction
6. Market Landscape
7. Market Segmentation by Product
8. Market Segmentation by End-users
9. Buying Criteria
10. Market Growth Drivers
11. Drivers and their Impact
12. Market Challenges
13. Impact of Drivers and Challenges
14. Market Trends
15. Trends and their Impact
16. Vendor Landscape
17. Key Vendor Analysis       

Source:-http://www.businesswire.com/news/home/20140716005875/en/Research-Markets-Industrial-Automation-Control-DCS-PLC#.VF2c8mf6y1s